The present invention relates generally to the field of semiconductor devices and, more particularly, to the field of semiconductor devices known as integrated injection logic (IIL).
IIL is a bipolar logic family that integrates a vertically operating switching transistor with a laterally operating load transistor in a contiguous region of semiconductor. The IIL semiconductor device is of particular interest due to the fact that its construction is simpler, can be manufactured at higher yield, can be integrated more densely and may have smaller power delay product when compared with a conventional transistor-transistor logic (TTL) device. In the IIL device the load or lateral transistor is usually used as an injector for injecting minority carriers into the base region of the vertical or switching transistor. The input to such an IIL device is controlled while the minority carriers are injected into the base region of the switching transistor to thereby control the collector output of the vertical transistor which comprises the output of the ILL device.
Referring to FIG. 1 a prior art IIL device is shown in side view. The prior art IIL device 12 is formed on a lightly doped p-type semiconductor substrate 14. A heavily doped layer 16 of n-type semiconductor material is formed over the substrate 14. Then, a semiconductor layer 18 of n-type material is formed over the layer 16 usually by an epitaxial growth process. A heavily doped p-type region 20 is formed by diffusion in the n-type layer 18 as is another region 22 of p-type material. The heavily doped p-type region 20 serves as an injector region for injecting holes. Heavily doped n-type regions 24 are formed in the second p-type region 22. A passivating layer 26, usually of silicon dioxide, is formed over the surface of the layer 18 and, by known processes, windows over the doped regions are opened and filled with metal contacts. Specifically, the metal contact 28 is deposited through the window in passivating layer 26 above the heavily doped p-type region 20. Metal contact 30 is deposited through the window in the area above p-type region 22 and, finally, metal contacts 32, 34 and 36 are deposited in the windows formed above the heavily doped n-type regions 24. Thus, a lateral, load PNP transistor is obtained wherein the emitter 40, base 42 and collector 44 are comprised, respectfully, of the heavily doped p-type region 20, then n-type region 18 and the p-type region 22 as is illustrated. Also, a vertical, switching NPN transistor is formed wherein the emitter 43, base 46 and collectors 48 are comprised, respectfully, of the n-type layer 18, the p-type region 22 and the heavily doped n-type regions 24.
FIG. 2 illustrates the equivalent electronic circuit of the semiconductor device illustrated in FIG. 1 wherein transistor Q.sub.2 corresponds to the lateral PNP transistor and wherein the transistor Q.sub.1 corresponds to the vertical NPN transistor. As can be seen in FIG. 2, the base region of transistor Q.sub.2 and the emitter region of transistor Q.sub.1 are at the same potential as is indicated by the ground symbol. This common potential between these regions results from the coincident utilization of n-type layer 18 for the base of transistor Q.sub.2 and the emitter of transistor Q.sub.1. As can also be seen in FIG. 2, the collector region of transistor Q.sub.2 is shared with and coincident with the base region of transistor Q.sub.1.
Each integrated cell of IIL devices as illustrated in FIG. 1 is a self-contained logic element which can be interconnected according to wired-AND logic to other ILL cells. The IIL construction technique leads to a considerable reduction in area per logic cell because much of the surface area that is normally required for contacts, interconnections and device isolation can be saved. However, this increase in packing density is offset by a reduction in device performance due to the non-ideal geometry of the switching transistor Q.sub.1. The poor performance of Q.sub.1 can be attributed to its large base-emitter junction area as is illustrated by the dashed lines in FIG. 1 which is due to the inverted, collector-up orientation of the device combined with the unavoidably large area of the multiple collector. In the prior art structure illustrated in FIG. 1, it is not possible to interchange the emitter and collector regions to obtain the more conventional downward injection because of the electrical connection to the base of the lateral transistor Q.sub.2 through the underlying bulk semiconductor substrate 14, 16.